1. Field of the Invention
The present invention relates generally to communication circuits and, more particularly, to integrated circuits for differentially driving data over a communication cable.
2. Description of the Related Art
In recent years, there has been a continual push to increase data transfer rates between computers, and between computers and peripheral devices. To meet the demand for higher speed links, many designers have been using twisted-pair or twin-x shielded cables to complete a high speed link. An advantage of using twisted-pair or twin-x shielded cables is that they maintain good signal integrity, and therefore, have low noise characteristics and are less susceptible to cross talk. Although these cables have these advantages, the integrated circuits that drive the differential signals over the twisted-pair cables to a differential receiver have been found to generate unacceptable differential signal waveforms.
For ease of discussion, FIG. 1A is a simplified diagram of a serial data transmission system 10. The serial data transmission system 10 includes a system 1, that may be a semiconductor chip that has a conventional differential driver 12 for communicating an input signal 11 over a twisted-pair cable 16. As shown, the twisted-pair cable 16 is coupled to a system 2, which has a differential receiver 14. In this example, the twisted-pair cable 16 is a current carrying system, that is coupled to ground and a voltage source 20. Voltage source 20 is then coupled to a termination load "R", which is connected to the input of the differential receiver 14.
FIG. 1B shows the input signal 11 having a period of about 5 nanoseconds in a 200 MHz signal, which is provided to the differential driver 12. In an ideal situation, the output of the differential driver 12 would produce a differential signal 27 and 28 having a zero signal crossing at a voltage level 30, a 50% duty cycle, and equal rise and fall slew rates as shown in FIG. 1C. The ideal differential output signal 27 and 28 has a T.sub.1 and a T.sub.2 that are equal (i.e., T.sub.1 =T.sub.2 =2.5 ns), representing a 50% duty cycle, and signals 27 and 28 crossing halfway between "Vdd" and "Vdd-IR". Specifically, the zero signal crossing occurs at a point 32, a point 34, a point 36, etc. Unfortunately, conventional differential drivers 12 are not well optimized to produce the ideal output illustrated in FIG. 1C. That is, conventional differential drivers 12 have been found to produce output signals with substantial jitter, and therefore, do not produce a zero signal crossing, fail to produce a 50% duty cycle, and have unequal rise and fall slew rates.
For example, conventional differential drivers 12 may produce a differential signal 27' and 28' having a signal crossing at points 32', 34' and 36' as shown in FIG. 1D. However, the signal crossings are offset from the zero signal crossing point 30. That is, the signal crossing point 32' is offset from the zero signal crossing point 30 by an offset 37. Similarly, crossing point 34' is offset from the zero signal crossing 30 by an offset 38. Furthermore, the differential signal produced by the differential driver 12 does not produce a 50% duty cycle or equal rise and fall slew rates. Consequently, when the differential signal produced by the differential driver 12 lacks good signal integrity, a substantial amount of jitter will be communicated to the differential receiver 14. As a result, the differential receiver 14 and its associated receiver circuitry will require substantially more time to decipher whether a received signal is a digital 1 or a digital 0. In fact, if the jitter is large enough, the differential receiver 14 may introduce errors in the received data.
FIG. 1E shows a prior art phase lock loop (PLL) 50 that receives a system clock to enable detection of the incoming signal in conjunction with a serial-to-parallel converter 52. If the signal that is being received by the differential receiver 14 and passed to the serial-to-parallel converter 52 has a substantial amount of jitter, the receiving system will require more time to ascertain the digital level being received over the twisted-pair cable 16. As can be appreciated, because the receiving circuitry is required to work harder to accurately read the incoming signals generated by the differential driver 12, the system as a whole may find it difficult to function at higher speeds.
In view of the foregoing, there is a need for a high speed differential driver that can accurately produce a zero signal crossing, a 50% duty cycle, and equal rise and fall slew rates.